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List of ARM processors

(Redirected from ARM SecurCore)

"ARM8" redirects here. For the ARMv8-A architecture, see ARMv8-A. For the ARMv8-R architecture, see ARMv8-R.

This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.[1] Keil also provides a somewhat newer summary of vendors of ARM based processors.[2] ARM further provides a chart[3] displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM core families.

Processors

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Designed by ARM

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Product familyARM architectureProcessorFeatureCache (I / D), MMUTypical MIPS @ MHzReference
ARM1ARMv1ARM1First implementationNone
ARM2ARMv2ARM2ARMv2 added the MUL (multiply) instructionNone0.33 DMIPS/MHz
ARM2aSARMv2aARM250Integrated MEMC (MMU), graphics and I/O processor. ARMv2a added the SWP and SWPB (swap) instructionsNone, MEMC1a
ARM3First integrated memory cache4 KB unified0.50 DMIPS/MHz
ARM6ARMv3ARM60ARMv3 first to support 32-bit memory address space (previously 26-bit).
ARMv3M first added long multiply instructions (32x32=64).		None10 MIPS @ 12 MHz
ARM600As ARM60, cache and coprocessor bus (for FPA10 floating-point unit)4 KB unified28 MIPS @ 33 MHz
ARM610As ARM60, cache, no coprocessor bus4 KB unified17 MIPS @ 20 MHz
0.65 DMIPS/MHz		[4]
ARM7ARMv3ARM700coprocessor bus (for FPA11 floating-point unit)8 KB unified40 MHz
ARM710As ARM700, no coprocessor bus8 KB unified40 MHz[5]
ARM710aAs ARM710, also used as core of ARM71008 KB unified40 MHz
0.68 DMIPS/MHz
ARM7TARMv4TARM7TDMI(-S)3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM 26-bit addressingNone15 MIPS @ 16.8 MHz
63 DMIPS @ 70 MHz
ARM710TAs ARM7TDMI, cache8 KB unified, MMU36 MIPS @ 40 MHz
ARM720TAs ARM7TDMI, cache8 KB unified, MMU with FCSE (Fast Context Switch Extension)60 MIPS @ 59.8 MHz
ARM740TAs ARM7TDMI, cacheMPU
ARM7EJARMv5TEJARM7EJ-S5-stage pipeline, Thumb, Jazelle DBX, enhanced DSP instructionsNone
ARM8ARMv4ARM8105-stage pipeline, static branch prediction, double-bandwidth memory8 KB unified, MMU84 MIPS @ 72 MHz
1.16 DMIPS/MHz		[6][7]
ARM9TARMv4TARM9TDMI5-stage pipeline, ThumbNone
ARM920TAs ARM9TDMI, cache16 KB / 16 KB, MMU with FCSE (Fast Context Switch Extension)200 MIPS @ 180 MHz[8]
ARM922TAs ARM9TDMI, caches8 KB / 8 KB, MMU
ARM940TAs ARM9TDMI, caches4 KB / 4 KB, MPU
ARM9EARMv5TEARM946E-SThumb, enhanced DSP instructions, cachesVariable, tightly coupled memories, MPU
ARM966E-SThumb, enhanced DSP instructionsNo cache, TCMs
ARM968E-SAs ARM966E-SNo cache, TCMs
ARMv5TEJARM926EJ-SThumb, Jazelle DBX, enhanced DSP instructionsVariable, TCMs, MMU220 MIPS @ 200 MHz
ARMv5TEARM996HSClockless processor, as ARM966E-SNo caches, TCMs, MPU
ARM10EARMv5TEARM1020E6-stage pipeline, Thumb, enhanced DSP instructions, (VFP)32 KB / 32 KB, MMU
ARM1022EAs ARM1020E16 KB / 16 KB, MMU
ARMv5TEJARM1026EJ-SThumb, Jazelle DBX, enhanced DSP instructions, (VFP)Variable, MMU or MPU
ARM11ARMv6ARM1136J(F)-S8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), enhanced DSP instructions, unaligned memory accessVariable, MMU740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz[9]
ARMv6T2ARM1156T2(F)-S9-stage pipeline, SIMD, Thumb-2, (VFP), enhanced DSP instructionsVariable, MPU[10]
ARMv6ZARM1176JZ(F)-SAs ARM1136EJ(F)-SVariable, MMU + TrustZone965 DMIPS @ 772 MHz, up to 2,600 DMIPS with four processors[11]
ARMv6KARM11MPCoreAs ARM1136EJ(F)-S, 1–4 core SMPVariable, MMU
SecurCoreARMv6-MSC000As Cortex-M00.9 DMIPS/MHz
ARMv4TSC100As ARM7TDMI
ARMv7-MSC300As Cortex-M31.25 DMIPS/MHz
Cortex-MARMv6-MCortex-M0Microcontroller profile, most Thumb + some Thumb-2,[12] hardware multiply instruction (optional small), optional system timer, optional bit-banding memoryOptional cache, no TCM, no MPU0.84 DMIPS/MHz[13]
Cortex-M0+Microcontroller profile, most Thumb + some Thumb-2,[12] hardware multiply instruction (optional small), optional system timer, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions0.93 DMIPS/MHz[14]
Cortex-M1Microcontroller profile, most Thumb + some Thumb-2,[12] hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memoryOptional cache, 0–1024 KB I-TCM, 0–1024 KB D-TCM, no MPU136 DMIPS @ 170 MHz,[15] (0.8 DMIPS/MHz FPGA-dependent)[16][17]
ARMv7-MCortex-M3Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions1.25 DMIPS/MHz[18]
ARMv7E-MCortex-M4Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv4-SP single-precision FPU, hardware multiply and divide instructions, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions1.25 DMIPS/MHz (1.27 w/FPU)[19]
Cortex-M7Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv5 single and double precision FPU, hardware multiply and divide instructions0−64 KB I-cache, 0−64 KB D-cache, 0–16 MB I-TCM, 0–16 MB D-TCM (all these w/optional ECC), optional MPU with 8 or 16 regions2.14 DMIPS/MHz[20]
ARMv8-M BaselineCortex-M23Microcontroller profile, Thumb-1 (most), Thumb-2 (some), Divide, TrustZoneOptional cache, no TCM, optional MPU with 16 regions1.03 DMIPS/MHz[21]
ARMv8-M MainlineCortex-M33Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processorOptional cache, no TCM, optional MPU with 16 regions1.50 DMIPS/MHz[22]
Cortex-M35PMicrocontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processorBuilt-in cache (with option 2–16 KB), I-cache, no TCM, optional MPU with 16 regions1.50 DMIPS/MHz[23]
ARMv8.1-M MainlineCortex-M521.60 DMIPS/MHz[24]
Cortex-M551.69 DMIPS/MHz[25]
Cortex-M853.13 DMIPS/MHz[26]
Cortex-RARMv7-RCortex-R4Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 8/12 regions1.67 DMIPS/MHz[27][28]
Cortex-R5Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP)[29]0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 12/16 regions1.67 DMIPS/MHz[27][30]
Cortex-R7Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP[29]0–64 KB / 0–64 KB, ? of 0–128 KB TCM, opt. MPU with 16 regions2.50 DMIPS/MHz[27][31]
Cortex-R8TBD0–64 KB / 0–64 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24 regions2.50 DMIPS/MHz[27][32]
ARMv8-RCortex-R52TBD0–32 KB / 0–32 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24+24 regions2.09 DMIPS/MHz[33]
Cortex-R52+TBD0–32 KB / 0–32 KB L1, 0–1 / 0–1 MB TCM, opt MPU with 24+24 regions2.09 DMIPS/MHz[34]
Cortex-R82TBD16–128 KB /16–64 KB L1, 64K–1MB L2, 0.16–1 / 0.16–1 MB TCM,

opt MPU with 32+32 regions

3.41 DMIPS/MHz[35][36]
Cortex-A
(32-bit)		ARMv7-ACortex-A5Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 FPU / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)4−64 KB / 4−64 KB L1, MMU + TrustZone1.57 DMIPS/MHz per core[37]
Cortex-A7Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), architecture and feature set are identical to A15, 8–10 stage pipeline, low-power design[38]8−64 KB / 8−64 KB L1, 0–1 MB L2, MMU + TrustZone1.9 DMIPS/MHz per core[39]
Cortex-A8Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / NEON / Jazelle RCT and DAC, 13-stage superscalar pipeline16–32 KB / 16–32 KB L1, 0–1 MB L2 opt. ECC, MMU + TrustZoneUp to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)[40]
Cortex-A9Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)16–64 KB / 16–64 KB L1, 0–8 MB L2 opt. parity, MMU + TrustZone2.5 DMIPS/MHz per core, 10,000 DMIPS @ 2 GHz on Performance Optimized TSMC 40G (dual-core)[41]
Cortex-A12Application profile, ARM / Thumb-2 / DSP / VFPv4 FPU / NEON / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)32−64 KB3.0 DMIPS/MHz per core[42]
Cortex-A15Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline[38]32 KB w/parity / 32 KB w/ECC L1, 0–4 MB L2, L2 has ECC, MMU + TrustZoneAt least 3.5 DMIPS/MHz per core (up to 4.01 DMIPS/MHz depending on implementation)[43][44]
Cortex-A17Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP32 KB L1, 256 KB–8 MB L2 w/optional ECC2.8 DMIPS/MHz[45]
ARMv8-ACortex-A32Application profile, AArch32, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline8–64 KB w/optional parity / 8−64 KB w/optional ECC L1 per core, 128 KB–1 MB L2 w/optional ECC shared[46]
Cortex-A
(64-bit)		ARMv8-ACortex-A34Application profile, AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–1 MB L2 shared, 40-bit physical addresses[47]
Cortex-A35Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–1 MB L2 shared, 40-bit physical addresses1.78 DMIPS/MHz[48]
Cortex-A53Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–2 MB L2 shared, 40-bit physical addresses2.3 DMIPS/MHz[49]
Cortex-A57Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline48 KB w/DED parity / 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses4.1–4.8 DMIPS/MHz[50][51][52]
Cortex-A72Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width superscalar, deeply out-of-order pipeline48 KB w/DED parity / 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses6.3-7.3 DMIPS/MHz[53][54]
Cortex-A73Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width superscalar, deeply out-of-order pipeline64 KB / 32−64 KB L1 per core, 256 KB–8 MB L2 shared w/ optional ECC, 44-bit physical addresses7.4-8.5 DMIPS/MHz[53][55]
ARMv8.2-ACortex-A55Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-width decode, in-order pipeline[56]16−64 KB / 16−64 KB L1, 256 KB L2 per core, 4 MB L3 shared3 DMIPS/MHz[53][57]
Cortex-A65Application profile, AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, out-of-order pipeline, SMT[58]
Cortex-A65AEAs ARM Cortex-A65, adds dual core lockstep for safety applications64 / 64 KB L1, 256 KB L2 per core, 4 MB L3 shared[59]
Cortex-A75Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-width decode superscalar, deeply out-of-order pipeline[60]64 / 64 KB L1, 512 KB L2 per core, 4 MB L3 shared8.2-9.5 DMIPS/MHz[53][61]
Cortex-A76Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way issue, 13 stage pipeline, deeply out-of-order pipeline[62]64 / 64 KB L1, 256−512 KB L2 per core, 512 KB−4 MB L3 shared10.7-12.4 DMIPS/MHz[53][63]
Cortex-A76AEAs ARM Cortex-A76, adds dual core lockstep for safety applications[64]
Cortex-A77Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 6-width instruction fetch, 12-way issue, 13 stage pipeline, deeply out-of-order pipeline[62]1.5K L0 MOPs cache, 64 / 64 KB L1, 256−512 KB L2 per core, 512 KB−4 MB L3 shared13-16 DMIPS/MHz[65][66]
Cortex-A78[67]
Cortex-A78AEAs ARM Cortex-A78, adds dual core lockstep for safety applications[68]
Cortex-A78C[69]
ARMv9-ACortex-A510
Cortex-A710[70]
Cortex-A715
Cortex-A520
Cortex-A720
Cortex-XARMv8.2-ACortex-X1Performance-tuned variant of Cortex-A78
ARMv9-ACortex-X2
Cortex-X3
Cortex-X4
NeoverseARMv8.2-ANeoverse N1Application profile, AArch32 (non-privileged level or EL0 only) and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 4-width decode superscalar, 8-way dispatch/issue, 13 stage pipeline, deeply out-of-order pipeline[62]64 / 64 KB L1, 512−1024 KB L2 per core, 2−128 MB L3 shared, 128 MB system level cache[71]
Neoverse E1Application profile, AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-wide decode superscalar, 3-width issue, 10 stage pipeline, out-of-order pipeline, SMT32−64 KB / 32−64 KB L1, 256 KB L2 per core, 4 MB L3 shared[72]
ARMv8.4-ANeoverse V1[73]
ARMv9-ANeoverse N2[74]
Neoverse V2[75]
ARMv9.2-ANeoverse N3[76]
Neoverse V3[77]
ARM familyARM architectureARM coreFeatureCache (I / D), MMUTypical MIPS @ MHzReference

Designed by third parties

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These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.

Product familyARM architectureProcessorFeatureCache (I / D), MMUTypical MIPS @ MHz
StrongARM
(Digital)		ARMv4SA-1105-stage pipeline16 KB / 16 KB, MMU100–233 MHz
1.0 DMIPS/MHz
SA-1100derivative of the SA-11016 KB / 8 KB, MMU
Faraday[78]
(Faraday Technology)		ARMv4FA5106-stage pipelineUp to 32 KB / 32 KB cache, MPU1.26 DMIPS/MHz
100–200 MHz
FA526Up to 32 KB / 32 KB cache, MMU1.26 MIPS/MHz
166–300 MHz
FA6268-stage pipeline32 KB / 32 KB cache, MMU1.35 DMIPS/MHz
500 MHz
ARMv5TEFA606TE5-stage pipelineNo cache, no MMU1.22 DMIPS/MHz
200 MHz
FA626TE8-stage pipeline32 KB / 32 KB cache, MMU1.43 MIPS/MHz
800 MHz
FMP626TE8-stage pipeline, SMP1.43 MIPS/MHz
500 MHz
FA726TE13 stage pipeline, dual issue2.4 DMIPS/MHz
1000 MHz
XScale
(Intel / Marvell)		ARMv5TEXScale7-stage pipeline, Thumb, enhanced DSP instructions32 KB / 32 KB, MMU133–400 MHz
BulverdeWireless MMX, wireless SpeedStep added32 KB / 32 KB, MMU312–624 MHz
Monahans[79]Wireless MMX2 added32 KB / 32 KB L1, optional L2 cache up to 512 KB, MMUUp to 1.25 GHz
Sheeva
(Marvell)		ARMv5Feroceon5–8 stage pipeline, single-issue16 KB / 16 KB, MMU600–2000 MHz
Jolteon5–8 stage pipeline, dual-issue32 KB / 32 KB, MMU
PJ1 (Mohawk)5–8 stage pipeline, single-issue, Wireless MMX232 KB / 32 KB, MMU1.46 DMIPS/MHz
1.06 GHz
ARMv6 / ARMv7-APJ46–9 stage pipeline, dual-issue, Wireless MMX2, SMP32 KB / 32 KB, MMU2.41 DMIPS/MHz
1.6 GHz
Snapdragon
(Qualcomm)		ARMv7-AScorpion[80]1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 FPU / NEON (128-bit wide)256 KB L2 per core2.1 DMIPS/MHz per core
Krait[80]1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON (128-bit wide)4 KB / 4 KB L0, 16 KB / 16 KB L1, 512 KB L2 per core3.3 DMIPS/MHz per core
ARMv8-AKryo[81]4 cores.?Up to 2.2 GHz

(6.3 DMIPS/MHz)

Ax
(Apple)		ARMv7-ASwift[82]2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEONL1: 32 KB / 32 KB, L2: 1 MB shared3.5 DMIPS/MHz per core
ARMv8-ACyclone[83]2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64. Out-of-order, superscalar.L1: 64 KB / 64 KB, L2: 1 MB shared
SLC: 4 MB		1.3 or 1.4 GHz
ARMv8-ATyphoon[83][84]2 or 3 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64L1: 64 KB / 64 KB, L2: 1 MB or 2 MB shared
SLC: 4 MB		1.4 or 1.5 GHz
ARMv8-ATwister[85]2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64L1: 64 KB / 64 KB, L2: 2 MB shared
SLC: 4 MB or 0 MB		1.85 or 2.26 GHz
ARMv8-AHurricane and Zephyr[86]Hurricane: 2 or 3 cores. AArch64, out-of-order, superscalar, 6-decode, 6-issue, 9-wide
Zephyr: 2 or 3 cores. AArch64, out-of-order, superscalar.		L1: 64 KB / 64 KB, L2: 3 MB or 8 MB shared
L1: 32 KB / 32 KB. L2: none
SLC: 4 MB or 0 MB		2.34 or 2.38 GHz
1.05 GHz
ARMv8.2-AMonsoon and Mistral[87]Monsoon: 2 cores. AArch64, out-of-order, superscalar, 7-decode, ?-issue, 11-wide
Mistral: 4 cores. AArch64, out-of-order, superscalar. Based on Swift.		L1I: 128 KB, L1D: 64 KB, L2: 8 MB shared
L1: 32 KB / 32 KB, L2: 1 MB shared
SLC: 4 MB		2.39 GHz
1.70 GHz
ARMv8.3-AVortex and Tempest[88]Vortex: 2 or 4 cores. AArch64, out-of-order, superscalar, 7-decode, ?-issue, 11-wide
Tempest: 4 cores. AArch64, out-of-order, superscalar, 3-decode. Based on Swift.		L1: 128 KB / 128 KB, L2: 8 MB shared
L1: 32 KB / 32 KB, L2: 2 MB shared
SLC: 8 MB		2.49 GHz
1.59 GHz
ARMv8.4-ALightning and Thunder[89]Lightning: 2 cores. AArch64, out-of-order, superscalar, 7-decode, ?-issue, 11-wide
Thunder: 4 cores. AArch64, out-of-order, superscalar.		L1: 128 KB / 128 KB, L2: 8 MB shared
L1: 32 KB / 48 KB, L2: 4 MB shared
SLC: 16 MB		2.66 GHz
1.73 GHz
ARMv8.5-AFirestorm and Icestorm[90]Firestorm: 2 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Icestorm: 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 7-wide.		L1: 192 KB / 128 KB, L2: 8 MB shared
L1: 128 KB / 64 KB, L2: 4 MB shared
SLC: 16 MB		3.0 GHz
1.82 GHz
ARMv8.6-AAvalanche and BlizzardAvalanche: 2 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Blizzard: 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.		L1: 192 KB / 128 KB, L2: 12 MB shared
L1: 128 KB / 64 KB, L2: 4 MB shared
SLC: 32 MB		2.93 or 3.23 GHz
2.02 GHz
ARMv8.6-AEverest and SawtoothEverest: 2 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Sawtooth: 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.		L1: 192 KB / 128 KB, L2: 16 MB shared
L1: 128 KB / 64 KB, L2: 4 MB shared
SLC: 24 MB		3.46 GHz
2.02 GHz
ARMv8.6-AApple A17 ProApple A17 Pro (P-cores): 2 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Apple A17 Pro (E-cores): 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.		L1: 192 KB / 128 KB, L2: 16 MB shared
L1: 128 KB / 64 KB, L2: 4 MB shared
SLC: 24 MB		3.78 GHz
2.11 GHz
Mx
(Apple)		ARMv8.5-AFirestorm and IcestormFirestorm: 4, 6, 8 or 16 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Icestorm: 2 or 4 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 7-wide.		L1: 192 KB / 128 KB, L2: 12, 24 or 48 MB shared
L1: 128 KB / 64 KB, L2: 4 or 8 MB shared
SLC: 8, 24, 48 or 96 MB		3.2-3.23 GHz
2.06 GHz
ARMv8.6-AAvalanche and BlizzardAvalanche: 4, 6, 8 or 16 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Blizzard: 4 or 8 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.		L1: 192 KB / 128 KB, L2: 16, 32 or 64 MB shared
L1: 128 KB / 64 KB, L2: 4 or 8 MB shared
SLC: 8, 24, 48 or 96 MB		3.49 GHz
2.42 GHz
ARMv8.6-AApple M3Apple M3 (P-cores): 4, 5, 6, 10, 12 or 16 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Apple M3 (E-cores): 4 or 6 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.		L1: 192 KB / 128 KB, L2: 16, 32 or 64 MB shared
L1: 128 KB / 64 KB, L2: 4 or 8 MB shared
SLC: 8, 24, 48 or 96 MB		4.05 GHz
2.75 GHz
ARMv9-AApple M4Apple M4 (P-cores): 3 or 4 cores. AArch64, out-of-order, superscalar, 8-decode, ?-issue, 14-wide
Apple M4 (E-cores): 6 cores. AArch64, out-of-order, superscalar, 4-decode, ?-issue, 8-wide.		L1: 192 KB / 128 KB, L2: 16, 32 or 64 MB shared
L1: 128 KB / 64 KB, L2: 4 or 8 MB shared
SLC: 8, 24, 48 or 96 MB		4.40 GHz
2.85 GHz
X-Gene
(Applied Micro)		ARMv8-AX-Gene64-bit, quad issue, SMP, 64 cores[91]Cache, MMU, virtualization3 GHz (4.2 DMIPS/MHz per core)
Denver
(Nvidia)		ARMv8-ADenver[92][93]2 cores. AArch64, 7-wide superscalar, in-order, dynamic code optimization, 128 MB optimization cache,
Denver1: 28 nm, Denver2:16 nm		128 KB I-cache / 64 KB D-cacheUp to 2.5 GHz
Carmel
(Nvidia)		ARMv8.2-ACarmel[94][95]2 cores. AArch64, 10-wide superscalar, in-order, dynamic code optimization, ? MB optimization cache,
functional safety, dual execution, parity & ECC		? KB I-cache / ? KB D-cacheUp to ? GHz
ThunderX
(Cavium)		ARMv8-AThunderX64-bit, with two models with 8–16 or 24–48 cores (×2 w/two chips)?Up to 2.2 GHz
K12
(AMD)		ARMv8-AK12[96]???
Exynos
(Samsung)		ARMv8-AM1 ("Mongoose")[97]4 cores. AArch64, 4-wide, quad-issue, superscalar, out-of-order64 KB I-cache / 32 KB D-cache, L2: 16-way shared 2 MB5.1 DMIPS/MHz

(2.6 GHz)

ARMv8-AM2 ("Mongoose")4 cores. AArch64, 4-wide, quad-issue, superscalar, out-of-order64 KB I-cache / 32 KB D-cache, L2: 16-way shared 2 MB2.3 GHz
ARMv8-AM3 ("Meerkat")[98]4 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order64 KB I-cache / 64 KB D-cache, L2: 8-way private 512 KB, L3: 16-way shared 4 MB2.7 GHz
ARMv8.2-AM4 ("Cheetah")[99]2 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order64 KB I-cache / 64 KB D-cache, L2: 8-way private 1 MB, L3: 16-way shared 3 MB2.73 GHz
ARMv8.2-AM5 ("Lion")2 cores, AArch64, 6-decode, 6-issue, 6-wide. superscalar, out-of-order64 KB I-cache / 64 KB D-cache, L2: 8-way shared 2 MB, L3: 12-way shared 3 MB2.73 GHz

Timeline

edit

The following table lists each core by the year it was announced.[100][101]

YearClassic coresCortex coresNeoverse cores
ARM1-6ARM7ARM8ARM9ARM10ARM11MicrocontrollerReal-timeApplication
(32-bit)		Application
(64-bit)		Application
(64-bit)
1985ARM1
1986ARM2
1989ARM3
1992ARM250
1993ARM60
ARM610		ARM700
1994ARM710
ARM7DI
ARM7TDMI
1995ARM710a
1996ARM810
1997ARM710T
ARM720T
ARM740T
1998ARM9TDMI
ARM940T
1999ARM9E-S
ARM966E-S
2000ARM920T
ARM922T
ARM946E-S		ARM1020T
2001ARM7TDMI-S
ARM7EJ-S		ARM9EJ-S
ARM926EJ-S		ARM1020E
ARM1022E
2002ARM1026EJ-SARM1136J(F)-S
2003ARM968E-SARM1156T2(F)-S
ARM1176JZ(F)-S
2004Cortex-M3
2005ARM11MPCoreCortex-A8
2006ARM996HS
2007Cortex-M1Cortex-A9
2008
2009Cortex-M0Cortex-A5
2010Cortex-M4(F)Cortex-A15
2011Cortex-R4
Cortex-R5
Cortex-R7		Cortex-A7
2012Cortex-M0+Cortex-A53
Cortex-A57
2013Cortex-A12
2014Cortex-M7(F)Cortex-A17
2015Cortex-A35
Cortex-A72
2016Cortex-M23
Cortex-M33(F)		Cortex-R8
Cortex-R52		Cortex-A32Cortex-A73
2017Cortex-A55
Cortex-A75
2018Cortex-M35P(F)Cortex-A65AE
Cortex-A76
Cortex-A76AE
2019Cortex-A77Neoverse E1
Neoverse N1
2020Cortex-M55(F)Cortex-R82Cortex-A78
Cortex-X1[102]		Neoverse V1[103]
2021Cortex-A510
Cortex-A710
Cortex-X2		Neoverse N2
2022Cortex-M85(F)Cortex-R52+Cortex-A715
Cortex-X3
2023Cortex-M52(F)Cortex-A520
Cortex-A720
Cortex-X4
2024Cortex-R82AECortex-A520
Cortex-A520AE
Cortex-A720AE
Cortex-A725
Cortex-X925		Neoverse N3
Neoverse V3
Neoverse V3AE

See also

edit

References

edit
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Further reading

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See also: List of books about ARM Cortex-M
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